週次 |
日期 |
單元主題 |
第1週 |
09/15 09/16 |
Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra |
第2週 |
09/22 09/23 |
Ch 2 Boolean AlgebraCh 3 Boolean Algebra (cont’d) |
第3週 |
09/29 09/30 |
Ch 4 Application of Boolean Algebra |
第4週 |
10/06 10/07 |
Ch 5 Karnaugh Maps |
第5週 |
10/13 10/14 |
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
第6週 |
10/20 10/21 |
Quiz 1 Ch 8 Combinational Ckt Design (skip 8.1, 8.2) |
第7週 |
10/27 10/28 |
Ch 8 (cont’d) Ch 9 Multiplexers Decoders and PLD (skip 9.7) |
第8週 |
11/03 11/04 |
Ch 9 (cont’d) Verilog: Combinational Circuits (3:30-6:00pm) |
第9週 |
11/10 11/11 |
Midterm |
第10週 |
11/17 11/18 |
Ch 11 Latches and FF |
第11週 |
11/24 11/25 |
Ch 12 Registers and Counters |
第12週 |
12/01 12/02 |
Ch 13 Analysis of Clock Sequential Ckts |
第13週 |
12/08 12/09 |
Ch 14 Derivation of State Graphs and Tables ( Skip examples 2 and 3 in Sec. 14.3) |
第14週 |
12/15 12/16 |
Quiz 2 Ch 15 Reduction of State Tables (15.1, 15.2) |
第15週 |
12/22 12/23 |
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
第16週 |
12/29 12/30 |
Ch 18 Circuits for Arithmetic Op. (18.1-18.2) |
第17週 |
2012/01/05 2012/01/06 |
Supplementary materials |
第18週 |
2012/01/12 2012/01/13 |
Final |